Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by forming field oxide regions by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) to form a field oxide region. The insulating material is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop, to remove all the oxide over the active regions so that only the trenches are filled. The nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
It is difficult to planarize the insulating material, because the field oxide regions vary largely in size. For example, one trench may have a width as little as 0.25.mu., while an adjacent trench may be several microns wide. After the insulating material is deposited to fill the trenches and cover the polish stop, fissures called "seams" exist in the deposited insulating material above the smaller trenches, and indentations called "steps" exist in the upper surface of the insulating material above the large trenches, which steps are considerably deeper and wider than the seams. The presence of both seams and steps is problematic during polishing, in that the large amount of polishing required to remove the seams over the small features results in the removal of excess insulating material over the large features. This overpolishing of the insulating material above the large trenches produces undesirable "dishing" of the insulating material, resulting in a nonplanar insulating surface.
A conventional approach to the problem of simultaneously planarizing an insulating material over both large and small features comprises masking, etching and then polishing, as by CMP. This procedure is illustrated in FIGS. 1A-1C. Adverting to FIG. 1A, there is schematically illustrated substrate 11, pad oxide layer 12, polish stop 13, oxide liner 14, trenches 15, insulating layer 16, seams 17 and steps 18. Inverse source/drain photoresist mask 19 is formed on the insulating layer 16 to protect the seams 17 and steps 18 from overetching. Isotropic etching is then performed to remove most of the insulating material in the active areas (FIG. 1B) before the final chemical-mechanical polish, as shown in FIG. 1C.
Disadvantageously, the inverse source/drain mask 19 is a "critical mask"; i.e., it is extremely complex and difficult to design and use. Its creation requires a complicated algorithm to calculate the location of the steps and seams and to provide protective masking over them, since even seams over the smallest features must be protected while etching. Moreover, the complexity of the mask and its small features challenges the capabilities of the photolithographic process necessary to implement the mask, thereby increasing manufacturing costs and reducing production throughput. As design rules are reduced to as small as 0.18.mu. or less, the inverse source/drain mask becomes even more difficult and costly to design and use.
In copending application Ser. No. 08/992,490, filed Dec. 18, 1997, now U.S. Pat. No. 6,124,183, and copending application Ser. No. 08/992,491, filed Dec. 18, 1997, now U.S. Pat. No. 6,090,713, methods were disclosed for forming an STI structure by planarizing the insulating material using a simplified planarization mask. Copending application Ser. No. 08/992,490 discloses a method wherein after the insulating material is deposited, it is polished, as by CMP, such that the insulating material above the small trenches (i.e., at the seams) is planarized, then the insulating material is furnace annealed to increase the resistance of the seams to etching. Following annealing, a simplified photoresist planarization mask is applied to cover only the insulating material above the large trenches (i.e., the steps), and the unmasked portions of the insulating material are etched. The mask is then removed and the remaining insulating material is planarized, as by CMP.
Copending application Ser. No. 08/992,491 filed Dec. 18, 1997, now U.S. Pat. No. 6,090,713 discloses a method wherein after the insulating material is deposited, it is polished, as by CMP, such that the insulating material above the small trenches (i.e., at the seams) is planarized, then a second, thin layer of insulating material is deposited to fill the seams. Following the second deposition of insulating material, which effectively eliminates the seams, a simplified photoresist planarization mask is applied to cover only the insulating material above the large trenches (i.e., the steps), and the unmasked portions of the insulating material are etched. The mask is then removed and the remaining insulating material is planarized, as by CMP.
The methodologies disclosed in copending application Ser. No. 08/992,490, filed Dec. 18, 1997 and copending application Ser. No. 08/992,491, filed Dec. 18, 1997, now U.S. Pat. No. 6,090,713 simplify the planarization mask by providing for masking only the insulating material over the large trenches. Thus, the design and implementation of the required mask is facilitated. However, these methodologies still require a planarization mask and an etching procedure, followed by removal of the mask, before planarization can be completed.
There exists a need for a simplified, cost-effective method of manufacturing a semiconductor device with shallow trench isolation without the necessity of employing a mask for planarizing the field oxide.